Integrated circuit device
US10685960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2018 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Oct 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6213
Abstract
An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.