Semiconductor memory devices and methods for fabricating the same
US10685972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Sep 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.