Semiconductor memory devices

US10685977B2 · kind B2 · utility

Assignee

• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Jongwon Kim · Buk-myeon, KR
• Hyeong-Jun Park · Seoul, KR
• Hyunmin Lee · Braunschweig, DE
• Hojong Kang · Cheongju-si, KR
• Joowon Park · Seoul, KR
• Seungmin Song · Seoul, KR

Key dates

• Filing date: Dec 24, 2018
• Grant date: Jun 16, 2020
• Expiry date: Dec 24, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/50

Abstract

A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.