Semiconductor device structure having low Rdson and manufacturing method thereof
US10686071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2018 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Sep 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.