Digital high speed acquisition system for phase locked loops
US10686455B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Aug 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit to receive a digitized voltage controlled oscillator tuning voltage and to compare the digitized voltage controlled oscillator tuning voltage to the sum and difference of the tuning and offset voltages to produce a window bounded by the sum and difference of the tuning and offset voltages. The comparator circuit is further configured to generate control signals. A steering current circuit is coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.