Top plate sampling analog-to-digital converter (ADC) with residue amplifier non-linearity reduction
US10686461B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2018 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Dec 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.