Multi-format pipelined hardware decompressor
US10691361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2017 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Jul 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/6029
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data compression schemes may indicate the length of the compressed data block in a header or in the compressed data itself. If the start and end of the data block are known before the decoding process has completed by the decoding stage, a header processing stage can ‘skip ahead’ to the start of the next block to begin processing the header of the next block while the current block is still being decoded. Thus, the header processing stage and the decoding stage are operated concurrently. If the end of the compressed block is indicated in the compressed data itself the end of the data block is not known until the end of the compressed data block is reached. For these types of compressed data blocks, the header processing stage waits until the decoding stage finishes with the preceding block before processing the header of the current block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.