Transistor threshold voltage maintenance in 3D memory
US10691372B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Mar 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for maintaining threshold voltages of non-data transistors in a memory device. The memory device has a stack comprising alternating horizontal conductive layers and horizontal dielectric layers. A control circuit is configured to test a threshold voltage criterion of non-data transistors in response to a trigger condition being met with respect to an erase of a data memory cells in a first tier of the stack. The control circuit is configured move valid data out of a data memory cells in a second tier of the stack in response to a determination that the threshold voltage criterion is not met. The control circuit is configured to adjust threshold voltages of the non-data transistors after moving the valid data out of the second set of data memory cells such that the threshold voltage criterion is met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.