Encryption for XIP and MMIO external memories
US10691838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Dec 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode. Caches in XIP interfaces provide seamless access to multiple memories, or multiple portions of a single memory. The cryptography block is configured to encrypt and decrypt XIP data transfers to and from a first external memory device in the XIP mode, and to encrypt and decrypt MMIO data transfers to and from a second external memory device in the MMIO mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.