Secure electronic chip
US10691840B2 · kind B2 · utility
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20Claims
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Assignee
Inventors
Key dates
| Filing date | Apr 25, 2016 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Apr 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.