Interface method of memory system, interface circuitry and memory module
US10692566B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2017 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | May 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system may comprise a plurality of data strobe transfer paths assigned to a plurality of data transfer paths such that each of the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths. At least one selected data strobe transfer path is selected and data signals transferred through the plurality of data transfer paths are sampled using at least one data strobe signal transferred through the selected data strobe transfer path. Reliability of data communication is enhanced through a redundant data strobe scheme by assigning a plurality of data strobe transfer paths to a plurality of data transfer paths such that the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.