Fan-out semiconductor package
US10692818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/18
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member and having openings exposing at least portions of the redistribution layer; metal members disposed in the openings of the passivation layer and connected to the exposed redistribution layer; and electrical connection structures disposed on the passivation layer and connected to the metal members, wherein the electrical connection structures have heights hierarchically differentiated from one another depending on sizes of the metal members.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.