3-dimensional NOR string arrays in segmented stacks
US10692874B2 · kind B2 · utility
36Cited by
7References
4Claims
0Family size
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Key dates
| Filing date | Jun 12, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Jun 12, 2038 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC07C2523/72
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.