3D static RAM core cell having vertically stacked structure, and static RAM core cell assembly comprising same
US10692935B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 28, 2016 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Feb 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/611
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a 3D static RAM core cell having a vertically stacked structure, including six thin-film transistors each having a gate electrode, a source electrode and a drain electrode, the static RAM core cell including two switching thin-film transistors, each connected to a bit line and a word line to select recording and reading of data, and four data-storage thin-film transistors connected to a power supply voltage (Vdd) or a ground voltage (Vss) to record and read data, the static RAM core cell including a first transistor layer including two thin-film transistors selected from among the six thin-film transistors, a second transistor layer disposed on the first transistor layer and including two thin-film transistors selected from among the remaining four thin-film transistors, and a third transistor layer disposed on the second transistor layer and including the remaining two thin-film transistors, at least one electrode of the first transistor layer and at least one electrode of the second transistor layer being electrically connected to each other, and at least one electrode of the second transistor layer and at least one electrode of the third transistor layer being elect…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.