Reducing latch count to save hardware area for dynamic Huffman table generation
US10693493B1 · kind B1 · utility
3Cited by
14References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2019 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/6058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for reducing a latch count required for symbol sorting when generating a dynamic Huffman table. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. The accelerator further includes a Huffman encoder communicatively coupled to the LZ77 compressor. The Huffman encoder includes a bit translator. The accelerator further includes an output buffer communicatively coupled to the Huffman encoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.