Efficient clock forwarding scheme
US10698439B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | May 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain aspects, an apparatus includes a multiplexer having a first input, a second input, a select input, and an output, wherein the first input is configured to receive a first reference clock signal, the second input is configured to receive a second reference clock signal, and the select input is configured to receive a select signal. The multiplexer is configured to select one of the first and second reference clock signals based on the select signal, and output the selected one of the first and second reference clock signals at the output of the multiplexer. The apparatus also includes a clock driver having an input and an output, wherein the input of the clock driver is coupled to the output of the multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.