Methods and apparatus for augmented bus numbering
US10698849B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2015 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Nov 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for augmenting routing resources. In one exemplary embodiment, a Thunderbolt™ transceiver incorporates a Peripheral Component Interconnect Express (PCIe) bus that supports hot-plugging and hot-unplugging of peripheral devices. Unfortunately, for various backward compatibility reasons, existing PCIe bus enumeration protocols can quickly exhaust the PCIe routing resources (for example, PCIe bus numbers) resulting in undesirable consequences (for example, crashes, dead connections, etc.) The present disclosure describes schemes for augmenting the pool of PCIe bus numbers and dynamically re-assigning PCIe bus numbers, so as to eliminate the aforementioned concerns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.