Secure and efficient application data processing
US10698854B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Feb 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system architecture is provided and includes first and second processing units respectively communicative with an on-chip coherency unit and an accelerator communicative with the on-chip coherency unit. The accelerator is configured to execute an operation responsive to a call issued by one of the first and second processing units. The first processing unit is configured to set an asynchronous operation flag (AOF) to indicate that the second processing unit is to conduct an operation for the first processing unit. The second processing unit is configured to respond to the AOF by building scatter gather lists and subsequently issuing the call and feeding the scatter gather lists to the accelerator to facilitate execution of the operation by the accelerator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.