Plated metallization structures
US10699948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Nov 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.