Patent · US Active

Device disaggregation for improved performance

US10700094B2 · kind B2 · utility

4Cited by

0References

25Claims

0Family size

Assignee

Xcelsis Corporation · US

Inventors

Javier A. Delacruz · San Jose, US
Don Draper · Chanhassen, US
Jung Ko · Daejeon, KR
Steven Teig · Menlo Park, US

Key dates

Filing date	Oct 10, 2018
Grant date	Jun 30, 2020
Priority date	—
Expiry date	Dec 29, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/981
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.