Semiconductor device

US10700217B2 · kind B2 · utility

Assignees

• Kabushiki Kaisha Toshiba · JP
• Toshiba Electronic Devices & Storage Corporation · JP

Inventor

• Masato Izumi · Kawasaki, JP

Key dates

• Filing date: Dec 28, 2018
• Grant date: Jun 30, 2020
• Expiry date: Dec 28, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/126

Abstract

A semiconductor device includes second and third semiconductor layers provided on a first semiconductor layer. The second semiconductor layer includes a recess portion and an outer edge portion. The third semiconductor layer is away from the second semiconductor layer in a first direction along a first boundary between the first semiconductor layer and the recess portion. The second semiconductor layer has first and second distributions of a second conductivity type impurity at a vicinity of the first boundary and at a vicinity of a second boundary between the outer edge portion and the first semiconductor layer, respectively. The third semiconductor layer has a third distribution of a second conductivity type impurity at a vicinity of a third boundary between the first semiconductor layer and the third semiconductor layer. The first distribution is substantially same as the second distribution. The third distribution is substantially same as the second distribution.