Avoiding very low duty cycles in a divided clock generated by a frequency divider
US10700669B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | May 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.