CMOS image sensor with single photodiode compact pixel layout
US10701298B1 · kind B1 · utility
0Cited by
8References
20Claims
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Key dates
| Filing date | Jun 5, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Jun 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8037
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A rectangular image sensor array of shared pixel units fabricated by a CMOS technology, wherein each pixel unit has a photodiode, a transfer transistor, a floating drain, a source follower transistor, a reset transistor and an in-pixel ground contact. The floating diode is spaced at the minimum distance from a gate electrode of the source follower transistor as is allowed by the CMOS fabrication technology chosen to manufacture the image sensor array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.