System and method for associative power and clock management with instruction governed operation for power efficient computing
US10705589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2017 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Apr 6, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes an ARM core processor, a programmable regulator, a compiler, and a control unit, where the compiler uses a performance association outcome to generate a 2-bit regulator control values encoded into each individual instruction. The system can provide associative low power operation where instructions govern the operation of on-chip regulators or clock generator in real time. Based on explicit association between long delay instruction patterns and hardware performance, an instruction based power management scheme with energy models are formulated for deriving the energy efficiency of the associative operation. An integrated voltage regulator or clock generator is dynamically controlled based on instructions existing in the current pipeline stages leading to additional power saving. A compiler optimization strategy can further improve the energy efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.