Program verify adaptation for flash memory
US10705900B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2018 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Oct 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a system and method for providing program verify adaptation for flash memory. The method includes performing an adjustment iteration, which includes accessing error counts for respective N states of a plurality of memory cells, applying a weighting to the error counts based on a binary data coding for the N states, determining a state Smin of the N states having a minimum error count Emin from the error counts, determining a state Smax of the N states having a maximum error count Emax from the error counts, determining a difference between the Emax and the Emin satisfies an error count threshold, and adjusting, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states, wherein the adjusting is a decrement when Smin is less than Smax and an increment otherwise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.