Detecting and handling errors in a bus structure
US10705936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2016 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | May 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a system, a computer program product and a method for detecting and handling errors in a bus structure by obtaining error information from a plurality of hardware registers associated with a bus; in response to determining that a number of the errors in one or more hardware registers of the plurality of hardware registers exceeds a predetermined threshold, detecting performance of hardware devices corresponding to the one or more hardware registers; and in response to determining performance deterioration of one hardware device in the hardware devices corresponding to the one or more hardware registers, determining that an error occurs in the hardware device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.