Scalable processor-assisted guest physical address translation
US10705976B2 · kind B2 · utility
2Cited by
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21Claims
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Key dates
| Filing date | Jun 29, 2018 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Aug 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples include a processor including at least one untrusted extended page table (EPT), circuitry to execute a set of instructions of the instruction set architecture (ISA) of the processor to manage at least one secure extended page table (SEPT), and a physical address translation component to translate a guest physical address of a guest physical memory to a host physical address of a host physical memory using one of the at least one untrusted EPT and the at least one SEPT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.