Randomization of dangling nodes in a digital circuit design to mitigate hardware trojans
US10706181B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2017 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Jun 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are various technologies pertaining to randomizing logic associated with dangling nodes in a digital circuit design. A dangling node is an input to or output from a logic gate in the digital circuit design that is identified as not impacting a desired output of the digital circuit design. Randomizing the logic associated with a dangling node can include deleting a logic gate, adding a logic gate, replacing a logic gate with another logic gate, etc. Randomizing the logic associated with the dangling node prevents hardware trojans that may have been inserted into the circuit design from being implemented in a circuit that is generated based upon the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.