Patent · US Active

Methods for layout driven synthesis of transmission line routes in integrated circuits

US10706206B1 · kind B1 · utility

3Cited by

0References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Sutirtha Kabir · Chandler, US
Vishal Agarwal · Bothell, US
Reenee Tayal · Delhi, IN

Key dates

Filing date	Dec 14, 2018
Grant date	Jul 7, 2020
Priority date	—
Expiry date	Dec 14, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2115/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer may generate a record of a template associated with a schematic design corresponding to an integrated circuit design. The template may have one or more instances corresponding to one or more initial parameters associated with a chain of one or more transmission line components of the integrated circuit design. The computer may then modify content of the chain of one or more transmission line components in a circuit layout corresponding to the schematic design within the maximum range limit of the one or more initial parameters. The computer may update the one or more instances according to modified contents of the one or more transmission line components in the circuit layout.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.