Priority aware balancing of memory usage between geometry operation and file storage
US10706208B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Aug 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/1734
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic memory management method for layout verification tools that maximizes main memory usage and minimizes required disk storage capacity. Layout data generated during each given geometric operation is retained in main memory at the end of the given geometric operation. At the beginning of each new (current) geometric operation, an estimated amount of main memory required to perform the current geometric operation at peak processing speed is determined. When insufficient available main memory is available, a Central Balancer Module determines whether previously generated layout data can be moved from main memory to disk storage. Layout data file(s) are then selected based on minimizing the amount of transferred layout data needed to provide the required estimated amount. A Distributed File Manager then transfers the selected layout data file(s) from main memory to disk storage, thereby facilitating execution of the current geometric operation at peak operating speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.