Memory with symmetric read current profile and read method thereof
US10706918B2 · kind B2 · utility
3Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Apr 22, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Apr 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.