Patent · US Active

Testing for memory error correction code logic

US10706950B1 · kind B1 · utility

5Cited by

2References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Patrick Gallagher · Apalachin, US
Steven Lee Gregor · Owego, US

Key dates

Filing date	Jun 19, 2018
Grant date	Jul 7, 2020
Priority date	—
Expiry date	Sep 27, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/4402
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and methods disclosed herein provide for improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”). Embodiments provide for a masking element to inject one or more faults into the ECC logic during at least one of a manufacturing test (“MFGT”) and a power-on-self-test (“POST”), wherein, based on the injected faults, it can be determined if the ECC logic contains any errors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.