Interconnection structure and method for manufacturing same
US10707117B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 6, 2018 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Nov 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53209
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure teaches interconnection structures and methods for manufacturing the same. In one implementation, a method may include: providing a substrate structure, including: a substrate, an interlayer dielectric layer on the substrate, a plurality of first through holes running through the interlayer dielectric layer, and a first metal layer filling the plurality of first through holes; forming a through hole structural layer on the substrate structure, where a dual-damascene through hole structure included in the through hole structural layer includes: a second through hole and a third through hole in the through hole structural layer, and an opening on the second through hole and the third through hole, and a part of the through hole structural layer between the second through hole and the third through hole is exposed in the opening; filling a second metal layer in the second through hole and the third through hole, where an upper surface of the second metal layer is lower than an upper surface of the part of the through hole structural layer; etching the part of the through hole structural layer so that the upper surface of the part is lower than the upper surface …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.