Etch profile control of interconnect structures
US10707123B2 · kind B2 · utility
2Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2017 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Oct 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/05093
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.