Power-on reset circuit
US10707863B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Aug 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-on reset circuit is provided. During a power-on process of the power-on reset circuit, a threshold voltage of an output signal rstn jumping from a low level to a high level is adjusted by clamp of a voltage at a node c and voltage division between a first resistor and a second resistor, and is controlled to be greater than a threshold voltage of a metal oxide semiconductor device. During a power-off process of the power-on reset circuit, a threshold voltage of the output signal rstn jumping from the high level to the low level is adjusted by increasing a voltage at a node d by means of a third resistor and voltage division between the first resistor and the third resistor, and is controlled to be greater than the threshold voltage of the metal oxide semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.