Reconfigurable programmable integrated circuit with on-chip network
US10707875B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | May 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and computer programs are presented for routing packets on a network on chip (NOC) within a programmable integrated circuit. One programmable integrated circuit comprises a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, an internal network on chip (iNOC) comprising iNOC rows and iNOC columns, an external network on chip (eNOC) connected to the iNOC rows and the iNOC columns, and a field programmable gate array Control Unit (FCU) for configuring programmable logic in the plurality of clusters based on a first configuration received by the FCU. The FCU is connected to the eNOC, where the FCU communicates with the plurality of clusters via the iNOC and the eNOC. The FCU is configured for receiving a second configuration from the programmable logic in the plurality of clusters for reconfiguring a component of the programmable integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.