Method and apparatus for switched adaptive clocking
US10707877B1 · kind B1 · utility
6Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 27, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.