Patent · US Active

Freeze logic

US10712385B2 · kind B2 · utility

0Cited by

8References

17Claims

0Family size

Assignee

Cryptography Research, Inc. · US

Inventors

Michael Hutter · Walnut Creek, US
Matthew Pond Baker · San Francisco, US

Key dates

Filing date	Dec 1, 2016
Grant date	Jul 14, 2020
Priority date	—
Expiry date	Dec 1, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH04L9/003
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output maybe generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.