Prefetcher for delinquent irregular loads
US10713052B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Jun 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.