Processor cache with independent pipeline to expedite prefetch request
US10713172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | May 18, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory for a processor including an arbiter, a tag array and a request queue. The arbiter arbitrates among multiple memory access requests and provides a selected memory access request. The tag array has a first read port receiving the selected memory access request and has a second read port receiving a prefetch request from a prefetcher. The tag array makes a hit or miss determination of whether data requested by the selected memory access request or the prefetch request is stored in a corresponding data array. The request queue has a first write port for receiving the selected memory access request when it misses in the tag array, and has a second write port for receiving the prefetch request when it misses in the tag array. The additional read and write ports provide a separate and independent pipeline path for handing prefetch requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.