Fast Fourier transform architecture
US10713333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2015 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Dec 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2651
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.