Semiconductor structure and method for manufacturing the same
US10714433B2 · kind B2 · utility
1Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | May 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor structure includes the following operations. A wafer with an orientation mark at a first crystal orientation represented by a family of Miller indices comprising <ijk> is provided, wherein i2+ j2+ k2=2. A first chip and a second chip are connected to a first surface of the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. The direction is not parallel to the first crystal orientation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.