Low noise analog-to-digital converter
US10715160B1 · kind B1 · utility
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23References
22Claims
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Key dates
| Filing date | Sep 13, 2019 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Sep 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Noise sources in an ADC circuit can include kT/C noise of a sampling capacitor, noise coupling on to sampling capacitors from digital circuits, and amplifier noise. Also, charge injection from mismatch in sample switches can cause offsets. These various noise sources can be largely canceled or reduced using described techniques. As a result, the size of the sampling capacitors can be greatly reduced, while still achieving significantly improved noise performance and power efficiency for the overall converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.