Circuit for error correction and method of same
US10715180B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2019 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Apr 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2906
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for error correction comprises a first RS syndrome generator to generate a first RS syndrome for a RS(n, k) code according to a received symbol stream to be decoded, wherein k and n are respective the number of data symbols and the total number of code symbols in the received symbol stream to be decoded; a first decision unit communicatively coupled to the first RS syndrome generator and configured to determine whether there are at least N symbols in the first RS syndrome that equal 0, wherein N is related to a code distance of the RS(n, k) code; and a first adder communicatively coupled to the first decision unit and configured to output a corrected decoded codeword by adding the first RS syndrome to the received symbol stream to be decoded if there are at least N symbols in the first RS syndrome that equal 0.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.