Delay compensation using broadband gain equalizer
US10715361B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2019 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Aug 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An electronic circuit can include a gain adjustment circuit (e.g., a gain “equalizer” circuit), such as to compensate for a variation in insertion loss over a specified range of frequencies. For example, such a gain adjustment circuit can provide an insertion loss characteristic having a specified slope. Such a slope can include a positive slope where insertion loss increases with respect to frequency, or a negative slope where insertion loss decreases with respect to frequency, as illustrative examples. A gain equalization technique can be used to compensate for variation in insertion loss versus frequency between different circuit paths, such as in relation to a switchable delay line having two or more selectable paths, such as for phase shifting applications. A gain adjustment circuit can be configured to provide relatively flat or constant time-domain delay versus frequency, such as inhibiting or reducing dispersion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.