Efficient transport flow processing on an accelerator
US10715451B2 · kind B2 · utility
16Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2016 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | May 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data processing apparatus includes a host processor and a network interface controller (NIC), which is configured to couple the host processor to a packet data network. A memory holds a flow state table containing context information with respect to computational operations to be performed on multiple packet flows conveyed between the host processor and the network. Acceleration logic is coupled to perform the computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.