Enhancement of performance of ultra-reliable low-latency communication
US10716133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/0023
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The disclosure describes mechanisms for reliability enhancement on control channel and data channel and mechanisms in URLLC. An apparatus of a RAN node for URLLC includes baseband circuitry to configure at least one DCI for scheduling transmission of at least one PDSCH content having same information. For each DCI, the baseband circuitry determines a CORESET for transmitting the DCI. The disclosure further describes mechanisms for the support of low latency transmission in URLLC. To improve peak data rate and spectrum efficiency in FDD system, the RAN node configures a DCI for scheduling data transmission using blank resources of a self-contained slot structure. Further, CBG-based transmission with separate HARQ-ACK feedback is provided to configure a DCI for scheduling data transmission of a TB and to divide the TB into multiple CBGs, and to configure uplink control data to carry separate HARQ feedback for the CBGs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.