Factory reset apparatus and method
US10719106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2019 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Jul 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A factory reset apparatus includes a reset switch, a first power supply module, a flip-flop, and a CPU. The flip-flop includes a data input pin, a clock pin, and a true flip-flop output pin. The reset switch is connected to the data input pin, the first power supply module is connected to the clock pin, and the true flip-flop output pin is connected to the CPU. The reset switch generates a low-level reset signal when being pressed; the flip-flop receives an electrical signal from the clock pin. A rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the reset signal. The flip-flop outputs a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the reset signal. The CPU starts a factory reset operation according to the reset request signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.