Method and device for recognizing hardware errors in microprocessors
US10719416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2018 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Jan 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method/device for recognizing a microprocessor hardware error, including comparing a first application's first result, running on a first microprocessor, with a second application's second result, running on the first/second microprocessor, with a microcontroller, providing comparison strategies, the hardware error being recognized as a function of the comparison, the microcontroller receiving a first message from the first microprocessor, and receiving a second message from the first microprocessor if the second application runs on the first microprocessor, or receives a first message from the second microprocessor if the second application runs thereon, the first message containing first comparison strategy information and first result information of a first function calculation, the second message containing second comparison strategy information and second result information of a second function calculation, the first and second strategy information being compared, the first and second result information being compared if the information about the comparative strategy coincides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.