Placement and timing aware wire tagging

US10719654B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Manuel Beck · Bietigheim-Bissingen, DE
• Florian Braun · San Antonio, US
• Lukas Dällenbach · Altdorf, DE
• Heinz Josef Hemmes · Holzgerlingen, DE
• Jesse Peter Surprise · Highland, US
• Marvin von der Ehe · Herrenberg, DE

Key dates

• Filing date: Nov 28, 2017
• Grant date: Jul 21, 2020
• Expiry date: Mar 30, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.